STK391-020, S(1)
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Ordering number:ENN5169
Thick Film Hybrid IC
STK391-020
2-Channel Convergence Correction Circuit
(I
C
max = 6A)
Overview
The STK391-020 is a convergence correction circuit IC for
video projectors. It incorporates two output amplifiers in a
single package, making possible the construction of CRT
horizontal and vertical convergence correction output cir-
cuits for each of the RGB colors using ust three hybrid ICs.
Package Dimensions
unit:mm
4062
[STK391-020]
64.0
55.6
8.5
Applications
• Video projectors
3.6
Features
• 2 output amplifier circuits in a single package
• High maximum supply voltage (V
CC
max =
±
44V)
1
15
C/W)
• High temperature stability (good idling current tem-
perature compensation)
• Low correction coil inductance for improved oscillator
stability (up to f
H
= 64kHz)
• Pin compatible with the STK4274 for easy replacement
q
j-c=2.7
°
2.54
0.5
0.4
2.9
(10.02)
14
´
2.54=35.56
SANYO : SIP15
Specifications
Maximum Ratings
at Ta = 25˚C
P
S
C
R
U
M
s
v
V
C
m
±
V
M
c
c
I
C
T
1
2
2
6
A
T
r
q
j
T
1
2
2
(
t
2
˚C/W
J
t
T
1
˚C
O
t
T
1
˚C
˚C
S
t
T
–
t
+
Operating Characteristics
at Ta = 25˚C, Rg=50
W
, V
CC
=
±
24V
R
P
S
C
U
m
t
m
O
n
v
V
N
0
m
Q
c
I
C
2
4
m
N
v
V
N
–
0
+
m
O
d
t
t
D
f
t
w
i
V
O
=
1
µ
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
92099TH (KT)/80995HA (ID) No.5169–1/6
• Low thermal resistance (
STK391-020
Equivalent Circuit
Test Circuit
Vo : V
NO
is measured by connecting a VTVM.
V
N
is measured by connecting a DC voltmeter.
t
D
is measured by connecting an oscilloscope.
No.5169–2/6
STK391-020
No.5169–3/6
STK391-020
j-c
The heatsink design is determined by the maximum rat-
ings of several key parameters–Tj max, Tc max and
q
The power dissipation, Pd, is the sum of channel 1, Pd1,
and channel 2, Pd2, power dissipations.
q
j-c.
Pd max=Pd1 max+Pd2 max
• Tj max (junction temperature)
Tj max is dependent on the physical structure of each func-
tional element. A junction temperature exceeding this rat-
ing can lead to device deterioration and breakdown, so
the design must not exceed this rating.
• Tc max (operating substrate temperature)
Tc max is dependent on the materials used within an ele-
ment and on the circuit design, and should be selected on
the basis of reliability. Operation exceeding this value is
not guaranteed.
Therefore, form equation (1),
q
c-a<
Tc max – Ta max
Pd max
................................ (3)
the necessary heatsink resistance is determined (note that
Tc max=105
°
C)
The power dissipation per power transistor per channel, Pc,
is related to the transistor junction temperature by the fol-
lowing equation.
•
q
j-c (thermal resistance)
j-c is dependent on the heatsink design, which can vary
greatly. the heatsink necessary is determined by calcula-
tion using the maximum rating for Tj.
As Tj and Tc operating conditions are independent, the
heatsink must be designed to satisfy the maximum ratings
for both parameters.
q
Tj=Pd max
´q
c-a+Ta+Pc
´q
j-c ............................ (4)
where Tj cannot exceed Tj max=105
°
C. Therfore, in order
to maintain Tj below 150
°
C, a lower heatsink thermal re-
sistance,
q
c-a, is necessary to lower Tc.
Heatsink Design Considerations
In the expressions below Pd represents the operating IC
substrate internal power dissipation and Pc represents the
power dissipation per transistor. The heatsink thermal re-
sistance,
Heatsink Design Example
This example assumes the following worst-case conditions–
V
CC
H=
±
35V, V
CC
L=
±
25V, output coil L
Y
=80
m
H and
, Ip-o
max=0.6Ap-o (Ip-o (Ip-p=1.2A) sawtooth wave input, Io
(DC) max=0.6A DC input, both chanels operating, Ta
max=60
W
, current detector resistance R
NF
=4.7
W
c-a, required to dissipate the total power dissi-
pation, Pd, is determined as follows :
q
°
C (guaranteed maximum).
Condition 1: IC substrate temperature not to exceed 105
°
C
The channel1 power dissipation, Pd1, is given from Fig-
ures 1 and 2.
• Pd1 max=7.0W (AC) with sawtooth wave input
• Pd1 max=13.2W (DC) with DC input
As Pd1 max (AC) < Pd1 max (DC), the power dissipation
is greater with DC input. Also, lokking at the output tran-
sistor dissipation, Pc,
• Pc=0.5Pd1 with sawtooth wave input
• Pc=Pd1 with DC input (one side transistor continuously
ON)
the power dissipation is also higher with DC input. Ac-
cordingly, the heatsink design example below assumes DC
input. The power dissipation in the predriver stage is ig-
nored.
As Pd1 max=Pd2 max+13.2W, Pd max (both channels) is
given by.
Pd
´q
c-a+Ta<105
°
C (Tc max) ............................ (1)
Where Ta is the guaranteed maximum ambient tempera-
ture.
Condition 2: Power transistor junction temperature, Tj, not
to exceed 150
°
C
Pd
´q
c-a+Pc
´q
j-c+Ta<150
°
C (Tj max) .............. (2)
j-c is the power transistor thermal resistance per
transistor. Therefore, the heatsink design must satisfy both
these expression.
q
Design Process
A model circuit for a single channel in the STK319-020 is
shown below.
Pd max=Pd1 max+Pd2 max=26.4W
From equation (3) with Ta=60
°
C,
q
c-a=
Tc max – Ta
Pd max
=
105–60
26.4
= ........ 1.70
°
C/W
For a 2mm aluminum heatsink with no surface coating, the
necessary surface area, S, is given from Figure 3.
S=780cm
2
(28cm
´
28cm)
No.5169–4/6
Maximum Ratings
Tj max, Tc max,
R
Y
=0
Where
STK391-020
Also from equation (4), the output stage power transistor
jucntion temperature is given by
C.
However, an allowance for the predriver stage power dissi-
pation (transistors, resistors, etc.) should also be included
in the substrate internal power dissipation, Pd.
°
C derating below Tj max=150
°
Tj =Pd max
´q
c-a+Ta+Pc max
´q
j-c
=26.4
´
1.7+60+13.2
´
2.7
=140.5
°
C
No.5169–5/6
which provides a 9.5
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